The present invention relates to a register file having a plurality of general-purpose registers for temporarily storing data in a microprocessor or the like.
As one of the measures for enhancing the performance of a microprocessor, there has been recently proposed a register file using an arrangement of register windows. For example, "The SPARC Architecture Manual", Sun Microsystems Inc., Version 8, 1990, pp 23-27, sets forth the specifications of such a register file. According to the arrangement of such a register file, the register file having a plurality of general-purpose registers is divided, in whole or in part, into a plurality of windows, each window sharing some registers as double-address registers with the two adjacent windows. By switching the window, available registers are switched. The use of double-address registers located in the overlapping portion of two adjacent windows, enables data to be transmitted between procedures at high speed.
Each of the registers in each window is designated by an address to be determined by a combination of a window number which selects a window and a register address which indicates a relative position in a window. Each of the double-address registers has two different addresses. A window number is specified by a window number signal to be supplied from a window control circuit which controls increment and decrement of the current window No. A register address is specified by a register address signal to be supplied by a register address signal generating circuit based on register designating bits in an instruction from a microprocessor.
A conventional register file having the window arrangement above-mentioned, comprises an address converting circuit and a decoding circuit, in addition to memory cell arrays forming a plurality of general-purpose registers, and a window control circuit and a register address signal generating circuit which are of the types above-mentioned. In a register file having 64 registers for example, the address converting circuit is adapted to convert a window number signal and a register address signal into a 6-bit address signal by an operational processing. In view of the fact that each of double-address registers has two different addresses, the address converting circuit is adapted to convert different combinations of a window number signal and a register address signal into the same address signal. Based on a 6-bit address signal from the address converting circuit, the decoding circuit is adapted to assert one of 64 word lines to select a register in the memory cell arrays.
Thus, the conventional register file above-mentioned has the address converting circuit for executing an operational processing for converting a window number signal and a register address signal into an address signal. Accordingly, the time required for executing the operational processing leads to one of causes which prevent a register from being read at high speed.